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Memory map for ARMv8-M TrustZone SOC's

raghu.ncstate

Hello,

I was wondering what the memory map of an SOC that includes a ARMv8-M TrustZone enabled system would like. Is it fixed or is it variable ? Based on the ARMv8-M ARM, it appears that things like the SAU, MPU, NVIC etc are all memory mapped and are expected to be at fixed address. Does this mean there is one SAU and one MPU for an entire SOC even if it includes multiple ARMv8-M cores?

section b7.1 of the ARMv8-M ARM has a system address map which defines addresses and the memory properties. If this address map is fixed, why do we need an MPU which has configurable regions with different memory attributes ?

Thanks

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  • 0 in reply to Ed Player
    Ed, thanks for the great reply. I would like to clarify a few things for an SoC with MPU, SAU and Security Extensions:
    1) Since the SoC resets using the default memory map, is it appropriate to think of the MPU settings as an attributes override of the default memory map, once it is configured?
    2) Since each PE has its own MPU/SAU/NVIC and it is accessed through the PPB, I assume using the MPU/NVIC/SAU address in the default system address map, on different PE's, will access the MPU/NVIC/SAU of that particular PE?
    3) What if you have other masters on the SoC that are not processor cores ? How would the MPU/SAU's be configured for those masters ? is that implementation specific?
    4) Also what about interrupt routing to different PE's on an SoC with multiple Cortex-M33 cores for example? NVIC does not have GIC like registers to target interrupts to different cores.
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  • 0 in reply to Ed Player
    Ed, thanks for the great reply. I would like to clarify a few things for an SoC with MPU, SAU and Security Extensions:
    1) Since the SoC resets using the default memory map, is it appropriate to think of the MPU settings as an attributes override of the default memory map, once it is configured?
    2) Since each PE has its own MPU/SAU/NVIC and it is accessed through the PPB, I assume using the MPU/NVIC/SAU address in the default system address map, on different PE's, will access the MPU/NVIC/SAU of that particular PE?
    3) What if you have other masters on the SoC that are not processor cores ? How would the MPU/SAU's be configured for those masters ? is that implementation specific?
    4) Also what about interrupt routing to different PE's on an SoC with multiple Cortex-M33 cores for example? NVIC does not have GIC like registers to target interrupts to different cores.
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