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Cortex A9 (IMX6) : Enabling branch prediction aborts

Gopu

Hello,

I am using imx6 (cortex- A9) board, and my mmu environment is as follows
            mmu   - enabled
            L1 data cache - enabled
            L1 instruction cache - enabled
            D-side prefetch - enabled
            L2 cache - disabled
            Branch prediction - disabled

With this environment, my code runs for a longer time (more than 12 hours) with out any issues.
But, if I enable branch prediction, the code aborts in few seconds, at random addresses.
I am not able to understand what goes wrong.
Are there any special option which I have to consider while building my code.
I am using GCC as the compiler.


Note : In my code, I am using a static library, which was given by our vendor.

Any help would be great.

Thanks,

Gopu

 

Parents
  • 0 in reply to Gopu
    FYI: Some embedded firmware code is timing and order sensitive.

    For example:
    Original C working code. (test on another board/chips; it does not work on a new revision of SoCs)
    *p1 = A;
    *p2 = B;
    *p3 = C;

    *p1 = A;
    ADD_50_NOP_HERE_STILL_DOES_NOT_WORK.
    *p2 = B;
    *p3 = C;

    *p1 = A;
    ADD_100_NOP_HERE_THEN_WORK.
    *p2 = B;
    *p3 = C;


    *p1 = A;
    *p3 = C; // without delay; re-order p2 and p3 lines; then works too.
    *p2 = B;


    *p1=A;
    ISB; // add ISB then works too.
    *p2=B;
    *p3=B;
Reply
  • 0 in reply to Gopu
    FYI: Some embedded firmware code is timing and order sensitive.

    For example:
    Original C working code. (test on another board/chips; it does not work on a new revision of SoCs)
    *p1 = A;
    *p2 = B;
    *p3 = C;

    *p1 = A;
    ADD_50_NOP_HERE_STILL_DOES_NOT_WORK.
    *p2 = B;
    *p3 = C;

    *p1 = A;
    ADD_100_NOP_HERE_THEN_WORK.
    *p2 = B;
    *p3 = C;


    *p1 = A;
    *p3 = C; // without delay; re-order p2 and p3 lines; then works too.
    *p2 = B;


    *p1=A;
    ISB; // add ISB then works too.
    *p2=B;
    *p3=B;
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