Hello,
I am using imx6 (cortex- A9) board, and my mmu environment is as follows mmu - enabled L1 data cache - enabled L1 instruction cache - enabled D-side prefetch - enabled L2 cache - disabled Branch prediction - disabled
With this environment, my code runs for a longer time (more than 12 hours) with out any issues.But, if I enable branch prediction, the code aborts in few seconds, at random addresses.I am not able to understand what goes wrong. Are there any special option which I have to consider while building my code.I am using GCC as the compiler.
Note : In my code, I am using a static library, which was given by our vendor.
Any help would be great.
Thanks,
Gopu
Hello, Thanks for the response. I have invalidated the branch predictor at reset. And mmu is 1:1 mapping, and instruction memory doesn't change after enabling the mmu.
Kindly find the answers for your questions below.
1. Why you disable Branch prediction and L2 cache?
What is the original issue that you saw?
Root cause of your original issue could be "lots of possibilities..."
I have disabled L2cache, because the execution was slower, when I enabled L2 cache.
Disabled Brach prediction, because enabling results in data abort.
So, wanted to solve this branch prediction issue, before enabling the l2 cache.
What things did your try before?
Tried reducing the arm core clock frequency.
Tried disabling optimisation.
When there is a data abort, it looks r11 or r12 register is corrupted. r11 and r12 are stored and restored in interrupt context switch.
But these issues doesnt happen when branch brediction is disabled.
2. How many cores do you enabled?
Try enable just one core if your chip supports this feature.
I have enabled, only one core.
3. What is your system configuration?
Core clock frequency? - 996MHz
board reference clock? - 24MHz
clock for memory interface? - 528MHz DDR3
Try lower clock frequency of core cpu -
Today, I have tried by reducing the core clock to 800MHz. With this there is no data abort. Does this mean that,
lower clock frequency of memory interface - Default is 528MHz, but I have not tried reducing this.
4. Modify gcc option to -O0 (less optimization) - This is my current configuration
5. How many boards report the same issue ? - Tried in 3 boards, and all report the same
replace memory module? - Tried 3 different boards, but not the module
In the PMU module, vdd values were not properly configured for ARM core clock. After configuring this properly, we were able to solve this issue. Sorry for the late reply. Hope this helps someone in future.