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Cortex A9 (IMX6) : Enabling branch prediction aborts

Gopu

Hello,

I am using imx6 (cortex- A9) board, and my mmu environment is as follows
            mmu   - enabled
            L1 data cache - enabled
            L1 instruction cache - enabled
            D-side prefetch - enabled
            L2 cache - disabled
            Branch prediction - disabled

With this environment, my code runs for a longer time (more than 12 hours) with out any issues.
But, if I enable branch prediction, the code aborts in few seconds, at random addresses.
I am not able to understand what goes wrong.
Are there any special option which I have to consider while building my code.
I am using GCC as the compiler.


Note : In my code, I am using a static library, which was given by our vendor.

Any help would be great.

Thanks,

Gopu

 

Parents
  • 0 in reply to Shengliang
    Today, I have tried by reducing the core clock to 800MHz. With this there is no data abort. Does this mean that,

    When DDR3 is accessed by ARM core at 1GHz the data read by core looks faulty.
    Do I have to analyze further by reducing the DDR3 clock from 528MHz to 520MHz instead of reducing the core clock.

    I will check ur suggestions as well.
Reply
  • 0 in reply to Shengliang
    Today, I have tried by reducing the core clock to 800MHz. With this there is no data abort. Does this mean that,

    When DDR3 is accessed by ARM core at 1GHz the data read by core looks faulty.
    Do I have to analyze further by reducing the DDR3 clock from 528MHz to 520MHz instead of reducing the core clock.

    I will check ur suggestions as well.
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