We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
Hello Support,
In the Cortex-R5 TRM [Section 9.1.1 -- Bus ECC -- Chapter is Level Two Interface] I see the following statement:
"
It is possible that fatal, that is double-bit, ECC errors
might cause more data corruption. This can result in the CPU operating on corrupted data, or
behaving unpredictably, based on corrupted control or response signals.
In the Cortex-R7 TRM [Section 11.1 -- About L2 Interface] I am unable to find anything similar to above related to Bus ECC,
Can you please help me understand whether Bus ECC within Cortex-R7 implementation doesn't have that limitation as Cortex-R5 for AXI Level 2 Master Interface?
Thank you.
Regards
Pashan