Hello Support,
In the Cortex-R5 TRM [Section 9.1.1 -- Bus ECC -- Chapter is Level Two Interface] I see the following statement:
"
It is possible that fatal, that is double-bit, ECC errors
might cause more data corruption. This can result in the CPU operating on corrupted data, or
behaving unpredictably, based on corrupted control or response signals.
In the Cortex-R7 TRM [Section 11.1 -- About L2 Interface] I am unable to find anything similar to above related to Bus ECC,
Can you please help me understand whether Bus ECC within Cortex-R7 implementation doesn't have that limitation as Cortex-R5 for AXI Level 2 Master Interface?
Thank you.
Regards
Pashan
Hi Pashan,
It would be a difficult matter.
As for the ECC, and as for my case, I will search the word 'correction' in the TRM.
We can find the following descriptions
The processor uses Single Error Correction and Double Error Detection (SEC-DED) ECCs to detect and correct errors in the RAMs and on the AXI buses. A finite number of hard, that is, permanent errors can be detected and corrected with continued operation using dedicated error registers.
Furthermore, we can find the section "7.2 RAM protection" for more information with regard to the error correction.
As the results, in the case of Cortex-R7, with more than one bit errors, the processor would not be deadlock or fallen into the fatal states because the erroneous cache line would be ignored (after retrying some times).
Best regards,
Yasuhiko Koumoto.