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Confusion about exception level of ARMv8

Xinwei

Hi,

I am fairly new to ARM processor and start work with cortexA57 recently.  After reading the technical manual and programmer guide , I have some questions regarding the exception level of v8.

1. How does the exception level change from one to another ？

     According to the documents, the EL can only be changed on taking exception. And also when an exception happens, the EL can only changed to a higher level. Then , how is it changed from higher EL to lower EL ?  For example, on reset, the processor starts at EL3, then how does it switch to execute program on the other levels ? Could anyone give an example to show how the EL changes during a boot sequence ?

2. How to get the current EL value ?

    The document says the register PSTATE contains a field CurrentEL which indicates on which EL the processor is executing.  Is the PSTATE register only existed in Aarch64 execution state , or it is also existed in Aarch32 ?  If not, how to read current EL value from Aarch32 ?

Thanks in advance !

Best regards,

Xinwei

Parents
  • 0 in reply to Ash Wilding

    Hi Ash,

    Thank you for your support, by read over your answer, I can now understand more about changing execution/exception mode. But I still have some concerns, could you please teach me?

    --------------------------------------

    If the initial processor mode (execution mode) is AArch64 at EL3, then I change it to AArch32 at EL0 for 32bit application.

    • SPSR_EL3.M[4] = 'b1                (AArch32)
    • SPSR_EL3.M[2:0] = 'b0000      (User mode)

    So, what happen if an exception (ie. Abort) is taken at current mode (AArch32, EL0)? Follow your explanation, I guess that the exception mode will be changed into EL1, won't it? Or the processor will jump to exception code that defined by vector table of program running in EL0? (instead of jumping into EL1 vector table as Figure 3.6. AArch32 processor modes)

    And if so, when handling the exception (assume now we are in EL1), We have to specify for processor to return from EL1 to EL0, to continue the program at EL0 (AArch32), is it correct?

    --------------------------------------

    For your information, I am working on ARMv8.3 A76 core.

Reply
  • 0 in reply to Ash Wilding

    Hi Ash,

    Thank you for your support, by read over your answer, I can now understand more about changing execution/exception mode. But I still have some concerns, could you please teach me?

    --------------------------------------

    If the initial processor mode (execution mode) is AArch64 at EL3, then I change it to AArch32 at EL0 for 32bit application.

    • SPSR_EL3.M[4] = 'b1                (AArch32)
    • SPSR_EL3.M[2:0] = 'b0000      (User mode)

    So, what happen if an exception (ie. Abort) is taken at current mode (AArch32, EL0)? Follow your explanation, I guess that the exception mode will be changed into EL1, won't it? Or the processor will jump to exception code that defined by vector table of program running in EL0? (instead of jumping into EL1 vector table as Figure 3.6. AArch32 processor modes)

    And if so, when handling the exception (assume now we are in EL1), We have to specify for processor to return from EL1 to EL0, to continue the program at EL0 (AArch32), is it correct?

    --------------------------------------

    For your information, I am working on ARMv8.3 A76 core.

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