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Hi,
I am fairly new to ARM processor and start work with cortexA57 recently. After reading the technical manual and programmer guide , I have some questions regarding the exception level of v8.
1. How does the exception level change from one to another ？
According to the documents, the EL can only be changed on taking exception. And also when an exception happens, the EL can only changed to a higher level. Then , how is it changed from higher EL to lower EL ? For example, on reset, the processor starts at EL3, then how does it switch to execute program on the other levels ? Could anyone give an example to show how the EL changes during a boot sequence ?
2. How to get the current EL value ?
The document says the register PSTATE contains a field CurrentEL which indicates on which EL the processor is executing. Is the PSTATE register only existed in Aarch64 execution state , or it is also existed in Aarch32 ? If not, how to read current EL value from Aarch32 ?
Thanks in advance !
Best regards,
Xinwei
Hi Ash,
Thanks for your answers and examples!
Since I am working with cortexA57 in aarch32 state, is it correct that Aarch32 doesn't really have the concept of EL but only 'mode' ? I was trying to use 'MSR r0, CurrentEL' to read the EL value, but it doesn't even compile. I am using ARM C/C++ Compiler 4.9 . Could that be the problem ?
Thanks and best regards,
Hello Xinwei,
No problem
Ah, things work differently in AArch32 state. AArch32 is backwards compatible with legacy code (i.e. ARMv7-A) but not compatible with AArch64, which is why MRS r0, CurrentEL doesn't work.
AArch32's modes roughly map onto AArch64's exception levels, as shown by Figure 3.6 here, i.e.:
One key difference here, though, is that in AArch32 MON actually has the same level of privilege as SVC, ABT, IRQ, FIQ, UND, and SYS, whereas in AArch64 EL3 is more privileged than EL1.
When in AArch32 state you can read the current mode by reading the CPSR.M field, i.e. bits [3:0]. You can access CPSR from any mode other than USR like this:
MRS R0, CPSR
If you're running in USR mode then you can instead access a subset of the CPSR known as APSR:
MRS R0, APSR
But bits [3:0] of APSR are RES0 since you're in USR mode.
So let's say you want to drop from AArch64 EL3 to AArch32 EL2. You'd need to:
If you've instead configured your Cortex-A57 to reset into EL3 with EL3 being AArch32 (via the AA64nAA32[N:0] signal described here) then you'll need to follow the AArch32 / legacy ARMv7-A model for changing mode.
We have an equivalent Cortex-A Series Programmer's Guide for ARMv7-A that you may find useful in conjunction with the one I linked earlier.
Hope that helps,
Ash.
Ash, Thanks a lot for your explanation !
Thank you for your support, by read over your answer, I can now understand more about changing execution/exception mode. But I still have some concerns, could you please teach me?
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If the initial processor mode (execution mode) is AArch64 at EL3, then I change it to AArch32 at EL0 for 32bit application.
So, what happen if an exception (ie. Abort) is taken at current mode (AArch32, EL0)? Follow your explanation, I guess that the exception mode will be changed into EL1, won't it? Or the processor will jump to exception code that defined by vector table of program running in EL0? (instead of jumping into EL1 vector table as Figure 3.6. AArch32 processor modes)
And if so, when handling the exception (assume now we are in EL1), We have to specify for processor to return from EL1 to EL0, to continue the program at EL0 (AArch32), is it correct?
For your information, I am working on ARMv8.3 A76 core.