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can we delay read and write transactions(axi4) by providing delay in register slice?

PREET

Basically I want to provide delay of 15 clock cycles  for writing and reading through axi4 bus .Is it possible?

Parents
  • 0 in reply to PREET

    Hello,

    the environment is CPU and Flash or L2 cache path of a certain actual SoC.

    Why do you think the write does not work?

    Can you show me the write channel behavior of your environment?

    Do you have any timing diagram of the write transaction?

    Doesn't it issue the write interleaving?

    The write logic is not more difficult than the read.

    The main bad point of my previous logic was the priority of set/reset for the wcounter.

    Best regards,

    Yasuhiko Koumoto.

Reply
  • 0 in reply to PREET

    Hello,

    the environment is CPU and Flash or L2 cache path of a certain actual SoC.

    Why do you think the write does not work?

    Can you show me the write channel behavior of your environment?

    Do you have any timing diagram of the write transaction?

    Doesn't it issue the write interleaving?

    The write logic is not more difficult than the read.

    The main bad point of my previous logic was the priority of set/reset for the wcounter.

    Best regards,

    Yasuhiko Koumoto.

Children