We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
On "ARM Cortex -A Series Programmer’s Guide" , a piece of code is followed:
...
@ Invalidate TLB
MCR p15, 0, r1, c8, c7, 0
@ Branch Prediction Enable
MOV r1, #0
MRC p15, 0, r1, c1, c0, 0 @ Read Control Register configuration data
ORR r1, r1, #(0x1 << 11) @ Global BP Enable bit
MCR p15, 0, r1, c1, c0, 0 @ Write Control Register configuration data
Does the statement "MOV r1, #0" have any special intention? The value of r1 will be replaced by the next MRC instruction. Whether can the statement "MOV r1, #0" be deleted?
Can anyone help?
Thanks,
Feng
Hello,
thank you for your comment and I have just confirmed by the document.
However, before Cortex-A architecture appeared, <Rt> value which be 'ignored' for MCR instruction should be SBZ (i.e should be zero).
The restriction had been relaxed at Cortex-A.
Now I think 'MOV r1,#0' would be meaningless.
Otherwise it might be the compiler's convenience.
By using a GCC, the following source code as
main() { int r; asm volatile ("MCR p15, 0, %0, c8, c7, 0" : "=r" (r) : "0" (r)); }
generates
main: mov r3, #0 MCR p15, 0, r3, c8, c7, 0
although the variable is not initialised.
Best regards,
Yasuhiko Koumoto.
Thanks!!
I double checked the old ARM document, compiled your code and got the same results as yours. Thank you!
Wang Feng