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There is a statement 'For wrapping burst, the length of the burst must be 2,4,8 or 16 transfers.' in AXI Addressing option.
I cannot understand that why must be 2,4,8 or 16 transfers? Is there some design issue?
Hope someone can help,thank you!!
Best Regards,
Evelyn
Dear Pete,
Thank you for your reply,
I still confused about the bit field can be reduced you mentioned, since AxLen[3:0] is defined as fixed 4 bit field.
Moreover, is it true that the restriction of wrapping burst length has no relationship with the behavior of wrapping?
Thank you for your help,
> I still confused about the bit field can be reduced you mentioned, since AxLen[3:0] is defined as fixed 4 bit field.
Hmm, good point. In general power of two fields are easier to handle in the hardware, so this is still a somewhat pragmatic simplification for most uses, but it does indeed look like my idea above wasn't correct at least at the interface level (an AXI implementation which only handled wrap bursts could use a smaller internal bus, even if the interface expected 4 bits, if it knew that that this constraint was always true). Sorry for the confusion.
> Moreover, is it true that the restriction of wrapping burst length has no relationship with the behavior of wrapping?
IIRC you wrap around based on the natural size of the burst (e.g. a 64 byte burst will wrap on a naturally aligned 64 byte boundary in the middle of the burst, a 32 byte burst will wrap on a 32 byte naturally aligned boundary). However, I'm not 100% sure if this is a limitation of the protocol specification, or just the implementations I have seen.
Pete