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GCC support for R52plus+fpuv5-sp-d16

chong wang

Hi everyone,

We are using GCC 15.2 to compile our code, with the -mcpu and -mfpu configuration shown below.

We encountered an issue: when the -O1 optimization level is selected, the following GIC configuration code generates a VSTR instruction to write 64-bit data to the irouter register. This operation results in a Data Abort exception.

It looks like the VSTR instruction is supported under the specific configuration of the R52+ core.

So now we have no idea about what reason causes the data abort exception? Any insights would be greatly appreciated.

Regards

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  • 0 in reply to Ronan Synnott

    Ronan, thanks for your reply;-)

    The exception registers‘ values are shown below

    Document description:

    We would like to clarify the following:

    1. If the R52 is configured with SP FPU only, can we still use VSTR/VLDR instructions to access memory?

    2. Can the GIC IROUTER register (64-bit) be accessed via VSTR/VLDR instructions?

    3. What is the difference between VSTR and STRD? It seems that using STRD to access GIC 64-bit registers works fine. Why would VSTR cause a Data Abort while STRD does not?

    Thanks in advance!

Reply
  • 0 in reply to Ronan Synnott

    Ronan, thanks for your reply;-)

    The exception registers‘ values are shown below

    Document description:

    We would like to clarify the following:

    1. If the R52 is configured with SP FPU only, can we still use VSTR/VLDR instructions to access memory?

    2. Can the GIC IROUTER register (64-bit) be accessed via VSTR/VLDR instructions?

    3. What is the difference between VSTR and STRD? It seems that using STRD to access GIC 64-bit registers works fine. Why would VSTR cause a Data Abort while STRD does not?

    Thanks in advance!

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