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Hi All, I have two questions related to axi. In system, I have one master ,one interconnect and one slave.Q1: If master send write transaction to slave -> DMB-> send read transcation to slave, the order seem by slave should be same as older seem by master?Q2:How about If master don't use DMB, just wait bresp and then send read transcation. the order seem by slave is same as master? will it happen reorder case?Thanks a lot!
Q1: Can I make this conclusion: If master A sends write transcation -> interconnect -> slave , and wait brsp and send read transaction -> interconnect-> slave. Master use AXCACHE=4'b0000(device non-bufferable) to write/read transaction. Then,the order in slave's side must be same as master's side。Am I correct?
Q2: If master don't use AXCACHE=4'b0000, the order in slave's side may not be same as master's side?
Thank a lot!!
Broadly yes - but you should refer to the AMBA AXI specification (https://developer.arm.com/documentation/ihi0022/latest, A4.3 - Memory types) for the detailed description. For example, there is also a Normal Non-cacheable Non-Bufferable type.