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Hi All, I have two questions related to axi. In system, I have one master ,one interconnect and one slave.Q1: If master send write transaction to slave -> DMB-> send read transcation to slave, the order seem by slave should be same as older seem by master?Q2:How about If master don't use DMB, just wait bresp and then send read transcation. the order seem by slave is same as master? will it happen reorder case?Thanks a lot!
Thanks for reply.
But If the master write transaction to slave -> wait brsp and then send read transaction to slave. it can not ensure that the slave must receive the write transaction first and then read transaction? because interconnect may send brsp to master first, and the delay (from master write -> interconnect-> slave) may not same as (from master read -> interconnect-> slave) . In this case, the slave will receive read transaction and then write transaction, the order is not same as master's?
Tom T said:But If the master write transaction to slave -> wait brsp and then send read transaction to slave. it can not ensure that the slave must receive the write transaction first and then read transaction?
If what you have is one requester (master) connected directly to one completer (slave), then seeing BRESP would let the requester know that the transaction had reached the destination. But that's not typically how things are arranged, there's typically an interconnect between the requester and the responder Take the two example systems on this page:
https://developer.arm.com/documentation/102202/0300/AXI-protocol-overview
You have a set of requesters connected to an interconnect, with a set of completes also connected to the interconnect. In these examples, the BRESP that the requesters see is coming from the interconnect. Which leads to the question - when will the interconnect return BREP to the requestor? Does it wait for end device to respond, or will it do it early?
When the requestor sets up the transaction it uses the AxCACHE signals to specify how the transaction should be treated. See this page (scroll down to Cache support) https://developer.arm.com/documentation/102202/0300/Channel-signals for an overview. If the requester specified that it didn't want an early acknowledgement, then the interconnect should wait for the end device to send BRESP before BRESP is sent to the requester.
So there's a hardware and software side to the problem. Software needs to correctly describe (using memory types, barriers...) the memory ordering it wants and who/what needs to see that ordering. Hardware needs generate a set of traffic, using the options in AXI, that achieve what software asks for.
Q1: Can I make this conclusion: If master A sends write transcation -> interconnect -> slave , and wait brsp and send read transaction -> interconnect-> slave. Master use AXCACHE=4'b0000(device non-bufferable) to write/read transaction. Then,the order in slave's side must be same as master's side。Am I correct?
Q2: If master don't use AXCACHE=4'b0000, the order in slave's side may not be same as master's side?
Thank a lot!!
Broadly yes - but you should refer to the AMBA AXI specification (https://developer.arm.com/documentation/ihi0022/latest, A4.3 - Memory types) for the detailed description. For example, there is also a Normal Non-cacheable Non-Bufferable type.