Armv7-a TrustZone cps instruction Question

Hi, When I attempt to run arm-trusted-firmware on a Cortex-A7 processor with security extensions, the assembly instruction "cps #22" is executed, and then the processor's r8-lr registers become 0xdeadbeef. Is this the correct behavior of the processor? If not, what could be wrong here?


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  • First, it should be noted that the connection method used was "a board with a JTAG debug probe" rather than a specific model. The scenario was as follows: when the bl2 component of TFA (Trusted Firmware-A), operating at the EL3 exception level, was running on the SoC (System-on-Chip), the execution of the instruction "cps #22" — which switches the processor mode to Monitor mode — caused the values of the registers from r8 to lr to change to 0xdeafbeef.

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  • First, it should be noted that the connection method used was "a board with a JTAG debug probe" rather than a specific model. The scenario was as follows: when the bl2 component of TFA (Trusted Firmware-A), operating at the EL3 exception level, was running on the SoC (System-on-Chip), the execution of the instruction "cps #22" — which switches the processor mode to Monitor mode — caused the values of the registers from r8 to lr to change to 0xdeafbeef.

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