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Why in A64 the coprocessor is removed?

For the view of architecture, why the coprocessor is removed for A64 instruction set?

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  • Hi,

    Even in AArch32 the coprocessors are only conceptual, with the opcode space being used to access system registers (CP15), debug registers (CP14), and FP / NEON (CP10 & CP11). This is contrast to older versions of the architecture where there needed to be a way to access actual coprocessors in the system.

    In AArch64, the conceptual coprocessors have been removed and we now only access system registers using MSR/MRS instructions with the target register's name.

    Take for example CPACR_EL1, which is architecturally mapped to the AArch32 register CPACR. To access CPACR in AArch32 we need to use coprocessor instructions:

    MRC p15,0,<Rt>,c1,c0,2 ; Read CPACR into Rt

    MCR p15,0,<Rt>,c1,c0,2 ; Write Rt to CPACR

    Whereas to access CPACR_EL1 in AArch64 we just use the register name:

    MRS <Xt>, CPACR_EL1 ; Read CPACR_EL1 into Xt

    MSR CPACR_EL1, <Xt> ; Write Xt to CPACR_EL1

    Hope that helps,

    Ash.

Reply
  • Hi,

    Even in AArch32 the coprocessors are only conceptual, with the opcode space being used to access system registers (CP15), debug registers (CP14), and FP / NEON (CP10 & CP11). This is contrast to older versions of the architecture where there needed to be a way to access actual coprocessors in the system.

    In AArch64, the conceptual coprocessors have been removed and we now only access system registers using MSR/MRS instructions with the target register's name.

    Take for example CPACR_EL1, which is architecturally mapped to the AArch32 register CPACR. To access CPACR in AArch32 we need to use coprocessor instructions:

    MRC p15,0,<Rt>,c1,c0,2 ; Read CPACR into Rt

    MCR p15,0,<Rt>,c1,c0,2 ; Write Rt to CPACR

    Whereas to access CPACR_EL1 in AArch64 we just use the register name:

    MRS <Xt>, CPACR_EL1 ; Read CPACR_EL1 into Xt

    MSR CPACR_EL1, <Xt> ; Write Xt to CPACR_EL1

    Hope that helps,

    Ash.

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