I would like to understand the nature of unaligned transfers better in axi. The spec says
How are these to be understood for WRITE and READ requests separately?Consider an axi-manager issues a WRITE request for AWADDR = 0x09 AWLEN = 3 AWSIZE = 2 (32 bits) on a 32 bits of data channel. 1. How is WSTRB provided? a. Is it only 3 bits of WSTRB = 3'b111 on a 4 bit WSTRB lane? In such a case, should the WSTRB be assumed to be 4'b0111 and later appropriately handled inside the fabric implementation? b. Or does the manager send the appropriate WSTRB = 4'b1110 (which seems unlikely, as the manager is sending an unaligned address by a correct WSTRB)?Moving to READ requests for the same unaligned transfers. ARADDR = 0x09, ARLEN = 3 ARSIZE=2 (32 bits) on a 32 bits of data channel.
1. How should this request be handled? Align the address to 0x08 and the manager should consider Upper 3 bytes of data only?
Can someone explain how both these requests are to be handled or managed as a HDL developer?
Your response is highly appreciated.P.S.: AXI spec considered from IHI0022K issue.
So, can I draw the following conclusion?1. The manager very well knows that address is unaligned for 0x09 and still has to send a valid WSTRB of 4'1110 (for WRITE) or read appropriate bytes from RDATA lines
2. Suppose I want to use an APB subordinate (with AXI4 to APB bridge in between) the bridge has to take care of aligning the address to lower natural word address as APB is word addressable?
Yes to your first conclusion. WSTRB must always be valid for the AWADDR/AWSIZE/AWBURST combination.
For the second point, APB does not support unaligned transfers, so the AXI4 manager should be aware that it should not use unaligned transfers when accessing APB devices.
However as to what the AXI4 to APB bridge does when generating PADDR, that is implementation specific (whether it just passes AWADDR to PADDR, or else aligns it to the APB data bus width).