Hello
I'm facing a problem that the core runs on the NVM at first, then jump to the RAM code to do some operation for the same partition of the NVM. After the operation (code on the RAM) is completed, back the NVM for the following code execution. In the RAM code, the completion of the NVM operation is ensured by checking some status flag.
The Read-While-Write error for the NVM occurs when branch predictor (IMP_BPCTLR) is enabled, I/D cache disabled, instruction speculative access disable (ISPECDIS = 1) and instruction prefetch disabled (L1IPFCTL = 0).
Only when branch predictor (IMP_BPCTLR) is disabled, the RWW error would not happen.
Could you explain how the branch predictor in the Cortex-R52+ work to help us on the root cause analysis ?
Do the IMP_BPCTLR affect the return address prediction, like pop {... pc} ?
Thanks and regards, Grace
I think the branch predictor is a symptom rather than the cause of the problem. The architecture allows for speculative data accesses to any region marked as Normal and speculative instruction fetch to any region marked as executable. If you have a region that for some reason should not be speculatively accessed, then you need to mark it as Device and execute never (XN).
For your example I'd expect a sequence similar to this: