Hi Community!
■ Issue DescriptionErrors occur in the burst waveform when accessing external SRAM. The test conditions are as follows:
- MMU enabled
- Data cache disabled
- Page table of the external SRAM area set as cacheable (== write-back/read-write/allocate)
■ InquiryI'm inquiring whether it is permissible to access cacheable areas (== write-back/read-write/allocate) with the data cache disabled.
If anyone could help regarding this , then it would solve a long standing problem for me.
Regards
daehyunyoon said:I'm inquiring whether it is permissible to access cacheable areas (== write-back/read-write/allocate) with the data cache disabled.
By data cache disabled, do you meant that SCTLR_ELx.C is cleared to 0?
If so, yes - it is legal to access regions marked as cache-able in the MMU translation tables with C=0. In the Arm ARM (K.a) you want section D7.5.5 "Enabling and disabling the caching of memory accesses". That says that if you set SCTLR_ELx.C to 0 then the all stage 1 translations will come out as data non-cacheable (so, effectively overriding what you put in the tables).
From the software side you have to be careful to avoid accessing the location as both cacheable and non-cacheable. That can lead to some interest cache coherency problems.
I'm afraid this answer probably doesn't help much in understanding the error in your waveforms, sorry.