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Problems with  AXI4  write data channel

uestc

Hello:

    Suppose there are 2 masters(master0 and master1) and 2 slaves(slave0 and slave1) for AXI4. As AXI4 protocol has removed WID signal for write data channel，When slave0 has received wvaild which is pulled up afte  slave0 has both received master0's and master1's imfomation of the write address channel successfully，I'm having a problem that how can slave0 know  wdata from master0 or master1 .

   If anyone gives some ideas about my problem ，it  would be great.

thanks.

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