Hello:
Suppose there are 2 masters(master0 and master1) and 2 slaves(slave0 and slave1) for AXI4. As AXI4 protocol has removed WID signal for write data channel，When slave0 has received wvaild which is pulled up afte slave0 has both received master0's and master1's imfomation of the write address channel successfully，I'm having a problem that how can slave0 know wdata from master0 or master1 .
If anyone gives some ideas about my problem ，it would be great.
thanks.
Hello,
according to AMBA® AXI™ and ACE™ Protocol Specification ARM IHI 0022E (ID022613), there are the descriptions below.
A5.4 Removal of write interleaving support
As stated in AXI3 write data interleaving on page A5-81, AXI4 removes support for write data interleaving. In
AXI4, all write data for a transaction must be provided in consecutive transfers on the write data channel.
This means the WID is not supported in AXI4.
A5.4.1 Removal of WID
The removal of write interleaving makes the information conveyed on the WID signals redundant. All write data
must be in the same order as the associated write addresses.
AXI4 removes the WID signals, to reduce the pin-count of the interface.
This means a slave may handle the write transactions in order which AWVALID will be active.
Best regards,
Yasuhiko Koumoto.
hello,
Do you mean if slave0 has reccived master0's imfomation of the write address channel successfully but has not reccived imfomation of master0's write data channel , slave0 would not reccive master1's imfomation of the write address channe?
Thanks!
I'm not understand what situation are you afraid of?
The slave0 can get the master1's write data after accepting the master0's write data.
For the slave0 aspect, it is seen the sequential two writes came.
Do you mean if slave0 has received master0's imfomation of the write address channel successfully but has not received imfomation of master0's write data channel , slave0 would not reccive master1's imfomation of the write address channe?
No, the slave0 can receive both master0 and master1 addresses, if it has more than two address buffers.
I guess the interconnect has a responsibility to arrange write data from master0 and master1 so that slave0 receives them in the same order as write address request received.
Wataru Yamamoto
Hello Wataru-san,
you are right.
For the slave0, the interconnect is seen as a master and the master should also follow the AXI4 specs.
That is, the interconnect cannot make the write interleaving.
Thanks very much for your answers, it's very helpfu to me!
Best regards, !
uestc.