Hello:
Suppose there are 2 masters(master0 and master1) and 2 slaves(slave0 and slave1) for AXI4. As AXI4 protocol has removed WID signal for write data channel，When slave0 has received wvaild which is pulled up afte slave0 has both received master0's and master1's imfomation of the write address channel successfully，I'm having a problem that how can slave0 know wdata from master0 or master1 .
If anyone gives some ideas about my problem ，it would be great.
thanks.
hello,
Do you mean if slave0 has reccived master0's imfomation of the write address channel successfully but has not reccived imfomation of master0's write data channel , slave0 would not reccive master1's imfomation of the write address channe?
Thanks!
Best regards,
Hello,
I'm not understand what situation are you afraid of?
The slave0 can get the master1's write data after accepting the master0's write data.
For the slave0 aspect, it is seen the sequential two writes came.
Do you mean if slave0 has received master0's imfomation of the write address channel successfully but has not received imfomation of master0's write data channel , slave0 would not reccive master1's imfomation of the write address channe?
No, the slave0 can receive both master0 and master1 addresses, if it has more than two address buffers.
Yasuhiko Koumoto.