Hello:
Suppose there are 2 masters(master0 and master1) and 2 slaves(slave0 and slave1) for AXI4. As AXI4 protocol has removed WID signal for write data channel，When slave0 has received wvaild which is pulled up afte slave0 has both received master0's and master1's imfomation of the write address channel successfully，I'm having a problem that how can slave0 know wdata from master0 or master1 .
If anyone gives some ideas about my problem ，it would be great.
thanks.
Hello,
I guess the interconnect has a responsibility to arrange write data from master0 and master1 so that slave0 receives them in the same order as write address request received.
Best regards,
Wataru Yamamoto
Hello Wataru-san,
you are right.
For the slave0, the interconnect is seen as a master and the master should also follow the AXI4 specs.
That is, the interconnect cannot make the write interleaving.
Yasuhiko Koumoto.