Architectures and Processors forum R5: Does the exception vector table reside in TCM if at 0x0000 0000

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R5: Does the exception vector table reside in TCM if at 0x0000 0000

Offline tjones95134 2 months ago

Hello,

If the R5's TCM is configured to reside at location 0x0000 0000 does it hold the exception vector table?

Thanks, Tom

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Ronan Synnott 2 months ago +2 verified

The vector table resides at either 0x0 or 0xffff0000, defined by a pin at reset, and reflected in the V bit of the SCTLR: https://developer.arm.com/documentation/den0042/a/ARM-Processor-modes-and-Registers...