The Cortex A9 FPU Technical Reference Manual describe the FPSCR register and says:
The exception flags, bit  and bits [4:0] of the FPSCR are exported on the DEFLAGS output so they can be monitored externally to the processor, if required.
The question is very simple: Where is DEFLAGS, How can I access this register?
My aim is to monitor the exception bits and throw an interrupt when an exception is detected.
Many thanks to all.
Hi there, I have moved your question to the Architectures and Processors forum. Many thanks.