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ARM SVE2 instruction to use 2048 bits vector

"Hi , I had recently installed DS5 and ran the matric multiplication application from SVE examples , since I had chosen the N1 as the FVP environment, I observed the vector length was 8 x 64 bits(since application had float 64 as datatype) = 512 bits. I am exploring more on how to force to use the predicate register to utilize the 2048 bits in SVE2 platforms "

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  • Did you mean the N1 or V1?

    Either way, SVE (and SVE2) is a scalable vector instruction set, supporting vector lengths from 128 to 20248 bits.  A given processor will have a maximum supported vector length, for example 256 bits.  You can use vector lengths below the maximum, but you can't above what the hardware supports.

    Software can written to be vector length agnostic, meaning that it will exploit whatever the configure (or maximum) vector length of the thing it is running on is.

    If you wanted to experiment with wider length lengths, the AEM (Architecture Envelope Model) might be useful.

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  • Did you mean the N1 or V1?

    Either way, SVE (and SVE2) is a scalable vector instruction set, supporting vector lengths from 128 to 20248 bits.  A given processor will have a maximum supported vector length, for example 256 bits.  You can use vector lengths below the maximum, but you can't above what the hardware supports.

    Software can written to be vector length agnostic, meaning that it will exploit whatever the configure (or maximum) vector length of the thing it is running on is.

    If you wanted to experiment with wider length lengths, the AEM (Architecture Envelope Model) might be useful.

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