Asking this to better understand how to manage cache consistency on I/O buffer for DMA read.
Is it possible that in between of cache invalidation on the buffer and end of DMA read, a speculative data access brings incomplete data to the cache?
When the cache on DMA read buffer (device to CPU) should be invalidated: before starting DMA, or after the DMA ends?
a.surati You are absolutely right, your link [2] exactly answers my question (I dismissed it on 1st reading, as it says it is about Cortex-A v8, while my question is about Cortex M v7).
The Microchip article [1] formally is correct - but misses the very important explanation on speculative line fills - why there should be a cache clean after the DMA.
The slide show by Mark Rutland [2] seems to provide the ultimate correct answer: clean the cache both before and after DMA read - but combined with his previous words about how complicated all this stuff is and will be more complicated in future - makes me look for simpler, more robust solutions. What you call a hammer, yes. I want my drivers to pass code review without questions.
But setting up a non-cached area in MPU is not so easy (must be synchronized with link script...) - after all, cache maintenance could be better for code robustness. MPU of CM7 is too limited.
Again thank you for pointing to these sources. Your answer has been noticed on the STM32 forum and it looks like some people there are surprised. Some of official STM32 libraries and examples are affected.