Hi,
I am migrating my application FW written in C from original target architecture of cortex-M4 to M7.
A piece of code that works on M4 now triggers an unaligned usage fault on M7, which does memcpy from peripherals region (BKPSRAM in the MCU) to the SRAM1.
The problem I am facing is rather intriguing...the fault would be triggered if the pointer of the destination memory is ODD, no problem if it is EVEN and no matter if it is aligned, and even if the pointer is ODD, there is no fault if the size of the data does not exceed 4 bytes.
The instruction that causes the fault is a LDR, which should support unaligned memory transfer.
Any idea is highly welcomed!
Is this question about STM32? If so, please see the default attributes of the memory map.
The BKPSRAM unfortunately is in a region that has "device" attribute. This can be fixed by defining a MPU region, or just avoid unaligned accesses there.
Hi Pavel,
Yeah I am aware of the aligned access requirement of the device region. But just curious as the device region is the source but not the destination.
I have tested memcpy with data size from 1 to 5 bytes, only failing from 5 bytes and more. Am just curious why would operations with 1 or 2 or 3 bytes did not cause any fault...
The LDR instruction that causes the exception - what is the operand size? is the source address aligned?