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Enable/Disable L2 cache on ARM Cortex-A72

Chanh

Hi all,

Is it possible to Enable/Disable L2 cache on ARM Cortex-A72? If yes could you please guide on how to do that?

Thanks a lot.

Parents
  • 0 in reply to 42Bastian Schick

    Hi Schick, I follow A72 TRM and do following step:

    Set Bit C and I of SCTLR_EL1 to 0

    Invalidate ICache

    Flush and Invalidate DCache

    May I know if this is enough or any other step is needed? I still can observe the timing increase a lot when I perform those steps.

    Btw, one more question, after I disable L1/L2 cache, I still set up MMU, is there any issue? Thanks.

Reply
  • 0 in reply to 42Bastian Schick

    Hi Schick, I follow A72 TRM and do following step:

    Set Bit C and I of SCTLR_EL1 to 0

    Invalidate ICache

    Flush and Invalidate DCache

    May I know if this is enough or any other step is needed? I still can observe the timing increase a lot when I perform those steps.

    Btw, one more question, after I disable L1/L2 cache, I still set up MMU, is there any issue? Thanks.

Children