Enable/Disable L2 cache on ARM Cortex-A72

Set Bit C and I of SCTLR_EL1 to 0

Invalidate ICache

Flush and Invalidate DCache

May I know if this is enough or any other step is needed? I still can observe the timing increase a lot when I perform those steps.

Btw, one more question, after I disable L1/L2 cache, I still set up MMU, is there any issue? Thanks.

Set Bit C and I of SCTLR_EL1 to 0

Invalidate ICache

Flush and Invalidate DCache

May I know if this is enough or any other step is needed? I still can observe the timing increase a lot when I perform those steps.

Btw, one more question, after I disable L1/L2 cache, I still set up MMU, is there any issue? Thanks.

Chanh said:

I still set up MMU, is there any issue?

I don't see any.

Chanh said:

I still can observe the timing increase a lot when I perform those steps.

Timing increase after disabling the cache? For sure. That's what caches are for!