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I wonder if the bit 22 has some function in instructions like LDRH, STRH, LDRSBT, LDRD, ... (bits 27, 26, 25 = 0, 0, 0)?
In some instructions, like LDR, STR, LDRB (bits 27, 26, 25 = 0, 1, 1) , I understand, it chooses between byte and word access.
Hello,
in legacy (or so called CISC) processors, the load or the move instruction included all addressing modes.
However, at RISC processors, it have come that the load and the move are thought different functions.
The move is used for the immediate or the register addressing.
The load (or store) is used for the memory addressing.
This would come from the load/store architecture.
The memory addressing will form "base register + immediate index" or "base register + (index register with shift)".
From the RISC view point, it would not be strange and it would be even normal.
The ARM specific feature would be that the memory addressing had the pre-indexed or post-indexed mode".
I am sorry but I cannot understand the meaning of "add r1, [r2], #imm".
ldr r1, [r2], #imm
would mean the following sequence because it was the post-indexed.
1) load a memory contents of [r2] into r1
2) add #imm to r2.
This would be simllar to the legacy processer's notation of "ldr r1,[r2++]".
In the "[r2++]" case, the incremented value is only the access size (i.e. 1 for byte, 2 for half-word and 4 for word).
In the ARM case, the indexing is generalized to be able to add any value specified by #imm.
Best regards,
Yasuhiko Koumoto.
With "ldr r1, [r2], #imm = add r1, [r2], #imm" I mean the architectures I'm more familiar with, not in "ARM language".