Bit 22 in some LD/ST instructions (Cortex-A7)

I, myself, am accustomed with the convention used with many other processors:

(6502, 68xx 68xxx, VAX11, PDP11, 8085, x86, PPC (I recall), ...)

stc; set carry - no operands => implied

ldr r, #val; the value 'val' is loaded into r - immediate

ldr r, address; the value in address 'address' is loaded into r - absolute

ldr r1, r2; the value of r2 is loaded into r1 - register(-direct)

ldr r1, [ r2]; the value pointed to by r2 is loaded into r1 - register indirect (or indexed)

ldr r1, [r2, #val]; the value pointed to by (r2 + #val) is loaded into r1 - indexed

ldr r1, [PC, #val]; the value pointed to by (PC + #val) is loaded into r1 - (PC-)relative

ldr r1, [r2++]; the value pointed to by r2 is loaded into r1, then r2 is incremented - indirect (or indexed) post-increment

...

The '[ ]' (sometimes '( )') usually means indirection, so

ldr r1, [r2], #imm would mean that imm would be added to the number pointed to by r2 and the result is loaded into r1.

(= add r1, [r2], #imm)

I don't recall encountering such instruction (whereas the 'add'-version is very familiar).

The ARM instruction set is, however, quite different also in philosophy, so different naming convention is

quite understandable.

I, myself, am accustomed with the convention used with many other processors:

(6502, 68xx 68xxx, VAX11, PDP11, 8085, x86, PPC (I recall), ...)

stc; set carry - no operands => implied

ldr r, #val; the value 'val' is loaded into r - immediate

ldr r, address; the value in address 'address' is loaded into r - absolute

ldr r1, r2; the value of r2 is loaded into r1 - register(-direct)

ldr r1, [ r2]; the value pointed to by r2 is loaded into r1 - register indirect (or indexed)

ldr r1, [r2, #val]; the value pointed to by (r2 + #val) is loaded into r1 - indexed

ldr r1, [PC, #val]; the value pointed to by (PC + #val) is loaded into r1 - (PC-)relative

ldr r1, [r2++]; the value pointed to by r2 is loaded into r1, then r2 is incremented - indirect (or indexed) post-increment

...

The '[ ]' (sometimes '( )') usually means indirection, so

ldr r1, [r2], #imm would mean that imm would be added to the number pointed to by r2 and the result is loaded into r1.

(= add r1, [r2], #imm)

I don't recall encountering such instruction (whereas the 'add'-version is very familiar).

The ARM instruction set is, however, quite different also in philosophy, so different naming convention is

quite understandable.

Hello,

in legacy (or so called CISC) processors, the load or the move instruction included all addressing modes.

However, at RISC processors, it have come that the load and the move are thought different functions.

The move is used for the immediate or the register addressing.

The load (or store) is used for the memory addressing.

This would come from the load/store architecture.

The memory addressing will form "base register + immediate index" or "base register + (index register with shift)".

From the RISC view point, it would not be strange and it would be even normal.

The ARM specific feature would be that the memory addressing had the pre-indexed or post-indexed mode".

I am sorry but I cannot understand the meaning of "add r1, [r2], #imm".

ldr r1, [r2], #imm

would mean the following sequence because it was the post-indexed.

1) load a memory contents of [r2] into r1

2) add #imm to r2.

This would be simllar to the legacy processer's notation of "ldr r1,[r2++]".

In the "[r2++]" case, the incremented value is only the access size (i.e. 1 for byte, 2 for half-word and 4 for word).

In the ARM case, the indexing is generalized to be able to add any value specified by #imm.

Best regards,

Yasuhiko Koumoto.

With "ldr r1, [r2], #imm = add r1, [r2], #imm" I mean the architectures I'm more familiar with, not in "ARM language".