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Cycle counter: on which ARM will the code successfully run?

Former Member
Former Member

On a Raspberry Pi 3b, which is ARM Cortex-A5 processor, ARMv7 architecture, I am reading the cycle counter registers from the PMU (Performance Monitor Unit):


uint32_t cycle_counter_read (void)
{
  uint32_t cc = 0;
  __asm__ volatile ("mrc p15, 0, %0, c9, c13, 0":"=r" (cc));
  return cc;
}

I'd like to understand on which ARM processors will this code run successfully, other than the one in Raspberry Pi 3B.

Which ARM info is important for this:

  • processor name (Cortex A5 only?)
  • architecture (ARMv7 only?)
  • aarch32 and/or aarch64?
  • the combination of the above?
  • something else?

Currently I have included this code only for ARMv7:

#if defined(PLATFORM_ARMV7) 

    cycle_counter_read();

#endif 

Thanks.

Parents
  • Hi Former Member,

    Note that RaspberryPi 3B has a 64b Armv8 Cortex-A53 CPU (more details here). It seems you might be running in 32b AArch32 mode, as is the case under RaspberryPi OS.

    The PMCCNTR register you are reading is fairly common. Quoting the architecture manuals:

    - It is present on Armv7-A/R CPUs implementing the Performance Monitors Extension.

    - It is also present on Armv8-A CPUs supporting AArch32 at EL0 and implementing FEAT_PMUv3 (in which case it corresponds to the low part of the AArch64 PMCCNTR_EL0 register).

    Best regards,

    Vincent.

Reply
  • Hi Former Member,

    Note that RaspberryPi 3B has a 64b Armv8 Cortex-A53 CPU (more details here). It seems you might be running in 32b AArch32 mode, as is the case under RaspberryPi OS.

    The PMCCNTR register you are reading is fairly common. Quoting the architecture manuals:

    - It is present on Armv7-A/R CPUs implementing the Performance Monitors Extension.

    - It is also present on Armv8-A CPUs supporting AArch32 at EL0 and implementing FEAT_PMUv3 (in which case it corresponds to the low part of the AArch64 PMCCNTR_EL0 register).

    Best regards,

    Vincent.

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