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clean and invalidate cache behavior before same address read

loquat

I am running on cortex-A17.

when following,

step1: STR  R0, [R1]       ; [R1] is cacheable

step2: DCCIMVAC          ; clean and invalidate cache

step3: LDR  R0, [R1]       ; memory read

Does step3 access L3(external memory) ?

Or access eviction-buffer in cortex-A17 ?

Or, unknown  behavior?

Parents
  • 0 in reply to Martin Weidmann

    Additional,

    step1: STR  R0, [R1]       ; [R1] is cacheable

    step2: DCCIMVAC          ; clean and invalidate cache

    step2': DMB (or DSB)     <- It's require?

    step3: LDR  R0, [R1]       ; memory read

    I am considering.

    For step3 read memory, step2'  is require.

    Or not require?

Reply
  • 0 in reply to Martin Weidmann

    Additional,

    step1: STR  R0, [R1]       ; [R1] is cacheable

    step2: DCCIMVAC          ; clean and invalidate cache

    step2': DMB (or DSB)     <- It's require?

    step3: LDR  R0, [R1]       ; memory read

    I am considering.

    For step3 read memory, step2'  is require.

    Or not require?

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