I am a junior ASIC engineer. At the moment, I have three the question about AMBA AXI 3.0
1. No combination paths between master and slave, all timing path must be registered. Why the VALID and READY signals can assert in the same time ?
2. In the FIXED burst address, If Start_Address = 0x48, Burst_length = 4, Burst_size = 4 --> can you calculate for me ?
3. If I have a FIXED bursts address, Can I read FIFO 8 times in a row ?
4. What the different between READ ADDRESS channel and WRITE ADDRESS channel ? can it combine into one channel ?
If you have figure illustrate, please show me !!!
Thank you so much.
Hi yahushikokoumoto,
Between a master and a slave (i.e. VALID and READY) should not be always registered
In the chapter 3.1 of the specification is "There must be no combination paths between input and output signals on both master and slave interfaces"
Hello,
the statements only say that a master and a slave must be able to work independently.
For example, READY input cannot be registered.
If it was registered, the de-assertion of VALID would delay and a salve misunderstood it as that one more request came.
Unless the VALID could be directly forwarded to the READY logic, the Figure 3-3 timing (it is also the same as shown by me) might impossible.
Best regards,
Yasuhiko Koumoto.
Thank Koumoto so much, I have already understood .