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I am a junior ASIC engineer. At the moment, I have three the question about AMBA AXI 3.0
1. No combination paths between master and slave, all timing path must be registered. Why the VALID and READY signals can assert in the same time ?
2. In the FIXED burst address, If Start_Address = 0x48, Burst_length = 4, Burst_size = 4 --> can you calculate for me ?
3. If I have a FIXED bursts address, Can I read FIFO 8 times in a row ?
4. What the different between READ ADDRESS channel and WRITE ADDRESS channel ? can it combine into one channel ?
If you have figure illustrate, please show me !!!
Thank you so much.
Thank Koumoto so much, I have already understood .