AXI4: Write-Alignemnent modes? Partial writing with write strobes possible?

Hello Martin,

although I am not Mr. Dave, I can answer.

This means addresses can be unaligned. But the Write-Strobes are always related to the aligned address, in this case 0x0 - right?

Yes.

Thanks for that information. When does this happen? Is this related to the Store Buffer capabilities (I'm on Cortex A9) ARM Information Center

If so, can this be disabled as described with Bit 11 in the Control Aux register?

From a slave view point, AWADDR is taken as aligned by AWSIZE.

If AWADDR[1:0]=01 and AWSTRB=0111, the salve will interpret them as AWADDR[1:0]=00 and AWSTRB=0111.

I think the store buffer never issue such irregular transaction.

That's interesting. Is there a possibility to signal the master, a slave does not support this kind of transfer although this is valid AXI spec?

I should be considered to build the system circuit when you implement it.

The designer should investigate AXI characteristics (or specs) of all masters and slaves.

Best regards.

Yasuhiko Koumoto.

Hello Martin,

although I am not Mr. Dave, I can answer.

This means addresses can be unaligned. But the Write-Strobes are always related to the aligned address, in this case 0x0 - right?

Yes.

Thanks for that information. When does this happen? Is this related to the Store Buffer capabilities (I'm on Cortex A9) ARM Information Center

If so, can this be disabled as described with Bit 11 in the Control Aux register?

From a slave view point, AWADDR is taken as aligned by AWSIZE.

If AWADDR[1:0]=01 and AWSTRB=0111, the salve will interpret them as AWADDR[1:0]=00 and AWSTRB=0111.

I think the store buffer never issue such irregular transaction.

That's interesting. Is there a possibility to signal the master, a slave does not support this kind of transfer although this is valid AXI spec?

I should be considered to build the system circuit when you implement it.

The designer should investigate AXI characteristics (or specs) of all masters and slaves.

Best regards.

Yasuhiko Koumoto.

This means addresses can be unaligned. But the Write-Strobes are always related to the aligned address, in this case 0x0 - right?

Yes

But does this mean the alignment is different for reading and writing? For reading it's bus-aligned but in writing it's AWSIZE-aligned?

Consider an address AWADDR=0x2

If awsize=1 (16 bit transfers), AWADDR[1:0]=10 and AWSTRB=0011, Would it then write address 0x2 and 0x3?

Does that mean for a 16-bit transfer, at most 2 neighbour bits in AWSTRB can be set to 1?

Best regards,

Martin

Hi Martin,

I'll just to expand a bit further on Yasuhiko Koumoto's reply with some additional points first.

Thanks for that information. When does this happen? Is this related to the Store Buffer capabilities (I'm on Cortex A9) ARM Information Center

If so, can this be disabled as described with Bit 11 in the Control Aux register?

That document is actually for the Level 2 Cache Controller (L2C-310), which is often used with the Cortex-A9, but may not necessarily be.

You are correct however that the store buffer in the Cortex-A9 is a good example of something that can cause partial write strobes. To give a simple example, if you were to perform the following writes to a Normal non-cacheable region of memory:

  MOV r0, #0x1000

  MOV r1, #1

  STRB r1, [r0]            ; Store the byte 0x01 to address 0x1000

  ADD r0, r0, #4

  MOV r2, #0xFF00

  STRH r2, [r0]            ; Store the halfword 0xFF00 to address 0x1004

Then these could be merged by the Cortex-A9's store buffer into a single AXI transaction with partial write strobes like so:

AWADDR: 0x1000

AWSIZE: 64-bit

WDATA: 0x0000FF00_00000001

WSTRB: 00110001

That's interesting. Is there a possibility to signal the master, a slave does not support this kind of transfer although this is valid AXI spec?

There isn't, and in this situation you must ensure that the master cannot issue transactions to the slave that it does not support. This is typically done by placing the slave in a region of memory that is marked as Strongly Ordered or Device type so that transactions will only be issued at program size (and cannot be merged).

But does this mean the alignment is different for reading and writing? For reading it's bus-aligned but in writing it's AWSIZE-aligned?

'Alignment' is always considered regarding the size of the transfer. For example, a 32-bit transfer of data is considered aligned when the address is a multiple of 4 bytes.

To try and explain unaligned transactions completely, let's look at some example data transfers that could take place when doing a transaction of two 32-bit transfers on a 32-bit bus to address 0x1. These would be the same whether it was a write or read transaction:

If this was a write transaction then the 'greying-out' of bits [7:0] is representative of the write strobes for the transfer - to reflect the unaligned address, WSTRB[0] is not set, and this data would not be written by the slave. So the first transfer of the burst writes to bytes 0x1, 0x2 and 0x3 only, then the second transfer of the burst is aligned and writes to 0x4->0x7.

If these data transfers were the result of a read transaction to address 0x1, then these data transfers would be the read data returned by the slave. Since the master issued the unaligned address, it will know that it was an unaligned transaction and it will simply ignore/discard the lowest byte of the first transfer.

Consider an address AWADDR=0x2

If awsize=1 (16 bit transfers), AWADDR[1:0]=10 and AWSTRB=0011, Would it then write address 0x2 and 0x3?

Does that mean for a 16-bit transfer, at most 2 neighbour bits in AWSTRB can be set to 1?

I'm afraid there's not much to say here other than yes, and yes

One point I will make though is that the write strobes are part of the write-data channel, not the write-address channel, so the signal is WSTRB (not AWSTRB). This is necessary as, like I said before, the write strobes can change for each write data transfer.

Dave

Thanks for that very detailed answer.

Great to have such a community!

That explains my question. There is still one left ;-)

You said, the alignment is always related to the size of the transaction.

If we consider a 32-bit bus, ARSIZE=1 (16 bit), ARADDR=0x2. Then this address is aligned with respect to arsize but not aligned to the bus size.

Read transactions always happen in width of the bus size. Will this now start reading at address 0x0, and the upper half word is the data of interest?

Best regards,

Robert

Thanks for that very detailed answer.

Great to have such a community!

I'm glad to hear it's of help

If we consider a 32-bit bus, ARSIZE=1 (16 bit), ARADDR=0x2. Then this address is aligned with respect to arsize but not aligned to the bus size.

This is correct.

Read transactions always happen in width of the bus size. Will this now start reading at address 0x0, and the upper half word is the data of interest?

Basically yes, the master will ignore the bottom two bytes of the data that is returned on RDATA, since it only asked for the upper half word.

Just as a side point - since the transaction has specified that the lower half word isn't needed, the slave doesn't necessarily have to return correct data for it - it could just drive these bytes with zeroes for example. Most slaves will still return the correct data for these bytes though.

Dave