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AXI4: Write-Alignemnent modes? Partial writing with write strobes possible?

Martin Trummer

Hi guys,

I have two questions related to the write-strobing in AXI4. Both examples work on a 32-bit bus.

First consider an unaligned access on address 0x1.

Can this access be created in 2 ways?

1) Addr=0x0, Wrstrb=1110

2) Addr=0x1, Wrstrb=0111

In the second question consider an aligned access to address 0x0 with 3 incremental bursts, awsize=32-bit.

Is it possible, that only parts of these 3 accesses get written due to a strobe pattern like the following: 1011 0010 0011

Thank you in advance!

Best regards,

Martin

Parents
  • 0 in reply to David Harriman-Smith

    Thanks for that very detailed answer.

    Great to have such a community!

    That explains my question. There is still one left ;-)

    You said, the alignment is always related to the size of the transaction.

    If we consider a 32-bit bus, ARSIZE=1 (16 bit), ARADDR=0x2. Then this address is aligned with respect to arsize but not aligned to the bus size.

    Read transactions always happen in width of the bus size. Will this now start reading at address 0x0, and the upper half word is the data of interest?

    Best regards,

    Robert

Reply
  • 0 in reply to David Harriman-Smith

    Thanks for that very detailed answer.

    Great to have such a community!

    That explains my question. There is still one left ;-)

    You said, the alignment is always related to the size of the transaction.

    If we consider a 32-bit bus, ARSIZE=1 (16 bit), ARADDR=0x2. Then this address is aligned with respect to arsize but not aligned to the bus size.

    Read transactions always happen in width of the bus size. Will this now start reading at address 0x0, and the upper half word is the data of interest?

    Best regards,

    Robert

Children
  • 0 Arm Employee Badge in reply to Martin Trummer

    Thanks for that very detailed answer.

    Great to have such a community!

    I'm glad to hear it's of help

    If we consider a 32-bit bus, ARSIZE=1 (16 bit), ARADDR=0x2. Then this address is aligned with respect to arsize but not aligned to the bus size.

    This is correct.

    Read transactions always happen in width of the bus size. Will this now start reading at address 0x0, and the upper half word is the data of interest?

    Basically yes, the master will ignore the bottom two bytes of the data that is returned on RDATA, since it only asked for the upper half word.

    Just as a side point - since the transaction has specified that the lower half word isn't needed, the slave doesn't necessarily have to return correct data for it - it could just drive these bytes with zeroes for example. Most slaves will still return the correct data for these bytes though.

    Dave