1. I READ the cortex-a78 trm, i confuse with the L1 Cache, what is VIPT behaves as PIPT? if L1 Cache is VIPT, Can it be understood as On a memory access operation, core get the physical addresses from L1 Cache first, if it do not hit ,than find the MMU?
2. what is the cache means? is it a contains L1 L2 L3 cache?
It means that software can handle the cache as PIPT, the cache micro architecture would solve the cache alias issue.
Why not use PIPT directly？