• State Accepted Answer
  • +1 person also asked this people also asked this
  • Locked Locked
  • Replies 1 reply
  • Subscribers 351 subscribers
  • Views 5192 views
  • Users 0 members are here
2025 survey

We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.

Options
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Cortex-A53 - Understanding Translation Table (Cannot enable MMU)

krjdev

Hello,

I'm trying to get MMU working on Cortex-A53. But still fails since at least 3 days. :(

I created following tables:

Level 1

Fullscreen
1
2
3
4
5
6
7
8
0 0000000010006003
1 0000000010007003
2 0000000010008003
3 0000000010009003
4 000000001000a003
5 0000000000000000
[...]
511 0000000000000000
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

Level 2

Table 0 @ 0x10006000 (DDR RAM)

Fullscreen
1
2
3
4
5
0 0000000000000701
1 0000000000200701
[...]
510 000000003fc00701
511 000000003fe00701
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

Table 1 @ 0x10007000 (DDR RAM)

Fullscreen
1
2
3
4
5
0 0000000040000701
1 0000000040200701
[...]
510 000000007fc00701
511 000000007fe00701
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

Table 2 @ 0x10008000T (DDR RAM)

Fullscreen
1
2
3
4
5
0 0000000080000701
1 0000000080200701
[...]
510 00000000bfc00701
511 00000000bfe00701
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

Table 3 @ 0x10009000 (DDR RAM)

Fullscreen
1
2
3
4
5
6
7
0 00000000c0000701
1 00000000c0200701
[...]
503 00000000fee00701
504 0000000000000000
[...]
511 0000000000000000
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

Table 3 @ 0x1000a000 (Memory-Mapped Devices)

Fullscreen
1
2
3
4
5
6
7
0 00000000ff000705
1 00000000ff200705
[...]
7 00000000ffe00705
8 0000000000000000
[...]
511 0000000000000000
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

The relevant setup for setup the pagetable:

Fullscreen
1
2
3
4
5
6
7
8
9
ldr x1, =0x3519
msr TCR_EL2, x1
mov x1, 0x00FF
msr MAIR_EL2, x1
ldr x1, =_tlb_el2_tbb0_lv1
msr TTBR0_EL2, x1
mov x8, xzr
dsb sy
ret
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

The relevant code for enabling the MMU:

Fullscreen
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
__el2_cache:
mrs x0, SCTLR_EL2
bic x0, x0, #(1 << 0) /* Disable MMU */
bic x0, x0, #(1 << 2) /* Disable D-Cache */
bic x0, x0, #(1 << 12) /* Disable I-Cache */
msr SCTLR_EL2, x0
isb
/* Invalidate and clean I/D-Cache */
bl _cpu_icache_invalidate
bl _cpu_dcache_l1_invalidate
bl _cpu_dcache_l2_invalidate
__el2_pagetable:
/* Create pagetable for EL2 */
bl _cpu_el2_tlb_create
/* Invalidate (old) Pagetable */
tlbi ALLE2
dsb sy
isb
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

I'm using U-Boot as bootloader (starting at EL2).

Have I something misunderstood? Have also tried several configurations. But still fails.

0