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Patent of ARM's single-cycle multiply on the M0+?

Hi,
    A few months ago I managed to find the appropriate patent as regards to the single-cycle multiply that is optional on the M0 & M0+. I've just spent 4 fruitless hours searching. IF I cannot get an MP3 decoder running on a 48MHz M0+ I might have to develop on an M1 to which a MULHS instruction is added. I seem to remember that it was either a ripple multiplier or a combinational logic multiplier. I noted that it uses around 8000 extra gates so I am guessing that it's actually 8192? A nice round hex number. 

Of course, I will also have to learn Verilog so I have ordered a couple of boks.

Many thanks,
Sean 

Parents
  • It's for a mobile product and the M0+ uses a tiny amount of power and costs pennies. Other have suggested that their is a 64MHz M0+ which I certainly will look at but I am keen to understand the single-cycle multiply. Thumb2 does have a MULH instruction so I want to know if such a thing would consume more power.

    I am aiming to produce an audio-book/audio-lesson for developing nations so the price-point it very important. 

Reply
  • It's for a mobile product and the M0+ uses a tiny amount of power and costs pennies. Other have suggested that their is a 64MHz M0+ which I certainly will look at but I am keen to understand the single-cycle multiply. Thumb2 does have a MULH instruction so I want to know if such a thing would consume more power.

    I am aiming to produce an audio-book/audio-lesson for developing nations so the price-point it very important. 

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