Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.
Recently, I read "AMBA AXI Protocol.pdf". but i have two questions about AXI after reading.
Firstly, i very wonder AWID, WID and BID when write transaction is started.
We assume that two masters(M0, M1-1bit ) and two slave(S0, S1) are.
The M0 master want to send the burst data to the S0 slave. the M0 master can generate the AWID( value : 0x0001 ). at that time, the M0 master must generate the WID corresponding AWID. I wonder this situation. is the WID value? simply, does the WID value have the same AWID value ( 0x0001) ? also, is the RID value? similarly, does the RID value have the same AWID value ( 0x0001) ?
Secondly, we assume that burst transaction is started.
Do WID and RID have to be generated whenever one of burst data is transferred or only one about all of the burst ?
I totally want to know about the situation.
Dear. Yasuhiko Koumoto
i understood that "it is just only the out-of-order response".
but i saw data interleaving in the first picture. also, in the second picture, A0 and A1 data are interleaved between B0 and B1.
is it possible??????
i think that it's impossible. because, in first picture, D31 and D32 data have to process in order without interleaving D11 ~D14 data. correct?
also i ask the two scenario. ( i assume that read transaction and all transaction have different IDs)
as you can see the first picture, i wrote "Data interleaving" . is it write data interleaving??
as you can see the second picture, i drawn the write transaction. is the scenario correct about Out-of-order and Write data interleaving in this picture?
please talk to me about correct information.
Hello,
but i saw data interleaving in the first picture. also, in the second picture, A0 and A1 data are interleaved between B0 and B1. is it possible??????
First of all, the data interleaving and the write interleaving are different concept.
So, it is possible.
The master should gather read response data corresponding to each address by using RID.
I will be possible.
How come are you so sure?
The D31 and D32 will be processed in order even with data interleaving of D11 to D14 because data response with RID of 0x001 are returned in order.
Why do you think " D31 and D32 data have to process in order without interleaving"?
I'm sorry but I cannot understand what the two scenario are.
The picture shows the tow write interleaving but what you indicate is a just the first data.
It might be said correct.
The picture also shows the two write interleaving.
Of course, it shows the out-of-order write response.
Please tell me what parts of my comments are incorrect.
I think I had shown no incorrect information.
Best regards,
Yasuhiko Koumoto.
Thank you for your solutions whenever i ask the AMBA 3.0 AXI.
i will enter the master's degree. so i don't have a lot of information about AXI.
Whenever i encounter the problem, i visit ARM community. And i post my problem on the community.
you are very kind, polite and good! your response is very helpful to me!
本当にありがとうございます。熱心に勉強します。
from In-Gyu.Lee