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Cortex-M3 Registers

Fabiano Junqueira

Hello guys.

I am studying the Cortex-M3 technical reference manual.

I have some doubts:
- What is the function of each of the 13 general purpose 32-bit registers, R0 to R12?
- What does Link Register (LR) do?
- What is the function of the xPSR register?
- What does the DebugReturnAdress() register do?
- What is the function of CONTROL, FAULTMASK, BASEPRI, PRIMASK of register 5b10100?

Thank you in advance!

Parents
  • 0 in reply to Andy Neil
    Thanks for the answer, but I don't know if my question was clear to you, because the links previously sent by you do not have the necessary content to solve my problem.

    I need help to make an application located in RAM run using instructions sent via SWD. I know that for this I will need to manipulate the registers "PC" "MSP" "R0" and some others. My question is not related to the SWD protocol. I already do the manipulations of the protocol correctly, because I can read the application that is in RAM and I have access to the registers "PC", "MSP" and "R0" via SWD.

    How should these registers ("PC", "MSP" and "R0") be handled for the application present in RAM to execute?

    Thank you!
Reply
  • 0 in reply to Andy Neil
    Thanks for the answer, but I don't know if my question was clear to you, because the links previously sent by you do not have the necessary content to solve my problem.

    I need help to make an application located in RAM run using instructions sent via SWD. I know that for this I will need to manipulate the registers "PC" "MSP" "R0" and some others. My question is not related to the SWD protocol. I already do the manipulations of the protocol correctly, because I can read the application that is in RAM and I have access to the registers "PC", "MSP" and "R0" via SWD.

    How should these registers ("PC", "MSP" and "R0") be handled for the application present in RAM to execute?

    Thank you!
Children