Hi,
I'm working on a project which is for debugging cortex-a53 through Jtag interface.
The Jtag clock TCK is set to 300kHz which is pretty low, and I can properly read back debug registers such as EDSCR and EDPRSR. EDPRSR is 1 before I issue the 'halt' request. My code will setup CTI and can successfully bring the core to halt state. At the halt state: EDPRSR would be read back as 0x11 (powered up, and halted, no OS lock, no OS double lock); EDSCR would be read back as 0x3C00313, which means: EDITR is ready to be written; INTdis is b'11, my code set that to avoid interrupt; TDA is 0, no trap for accessing debug register; MA=0, Normal access mode; NS=0, Secure state; SDD=0, Secure debug is enabled; HDE=0, Halting debug enable not set, as the halt is triggered from CTI but not BP/WP or HLT instruction; RW=b'0000, means all EL levels are AArch32 state; EL=3, which is current EL; A=0, no error interrupt pending; ERR=0, no Cumulative error; STATUS=b'010011, External debug request; So at this point, everything looks fine. However, if I do a write to EDITR with opcode as: MCR p14, 0, 0, c0, c5, 0 => 0xEE000E15 => read r0 EDSCR will be read back as: 0x3C00353, i.e. ERR bit would be set, neither overRun, nor underRun; Use MCR to read r0 should be legal and no exception should happen here; no interrupt; should be no permission issue, I think. So what else could go wrong? I'm bump to the wall for days now and have no clue so far. Really appreciate if you can shine some light on this. Thanks in advance,
SQU
Hello
I have a similiar Problem. The core is in HALTED state after I trigger the corresponding CTI event. OS Lock is also disabled.
After I write write an Opcode to EDITR I get the EDSCR::ERR bit is set. Here is the complete register dump:
EDSCR = 0x03000313 (before writing the opcode to EDITR)EDSCR = 0x03000353 (after write the opcode to EDITR)
0x03000313 (before writing the opcode to EDITR)
EDSCR = 0x03000353 (after write the opcode to EDITR)
0x03000353 (after write the opcode to EDITR)
My interpretation is that RW, bits[13:10] are zero which means T32 Mode.
I have tried different opcode:
T32 opcode: 0x091c //adds r1, r1, #0
and aslo 64bit
T64 opcode: 0xaa0103e1 //mov x1, x1
but the problem is the same. May there other prerequisites to execture instructions over EDITR
BR Martin
The main thing to note about executing instructions in Debug state is that not all instructions are allowed. Depending on the implementation, the processor might take an Undefined Instruction exception resulting in EDSCR.ERR being set.
For AArch32, none of the 16-bit T32 instructions are allowed. You need to look at sections H2.4.2 and H2.4.3 of the ARMv8 Architecture Reference Manual, which lists the instructions you can use. In particular, section H2.4.3 has some useful tables of instruction encodings. As the original posted noted, though, these tables show the half-words reversed compared to how you write the instruction to EDITR.
In general, arithmetic and register move instructions are also not allowed. Basically the set of instructions that are allowed are those needed to:
* Move general-purpose registers to and from the Debug Comms Channel registers
* Move general-purpose registers to and from Special-purpose, System and FP&SIMD registers, including extracting high/low parts of SIMD registers.
* Load/store registers from memory, including different sizes and different types of access.
* Barriers, clear exclusive, set event, cache & TLB maintenance.
thank you. now it works without the error flag is set
Thank you Michael. This helps. Do you know how can I read/write CPSR in debug state in aarch32?
MSR/MRS instructions are working for SPSR and ERR bit gets set when I read/write CPSR, i.e. 0xf3ff8000 (spsr) is working and 0xf3ef8000 is not working.
This is resolved now. MSR/MRS to/from CPSR are unallocated in debug state, using DSPSR instead.