This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

How to verify the Cortex-M0 thumb instructions ? I found one chip( RAM &FLASH is OK) when it run LDR relative instructions,the program is in Hardfault。But others run the same code is OK

Could you help me to solve the problem.Do  you have the code  to verify the thumb instruction ? If have,the code can check any  corner the functions of thumb instructions

Parents
  • For chip production tests, usually for logic (i.e. the processor and the processor system logic excluding RAM) should be tested using scan tests. Before tape out, you should also run LEC (Logic Equivalent Checking) to ensure that that netlist matching the RTL.

    For memory macros, you can add memory BIST (this is done outside of processors). You need to check the EDA tool manuals on how to do that. You could run software based memory tests, but there is an issue - if the chip is bad, how can you be sure the software to test memory is running correctly?

    If you google for "memory testing algorithms" you should find plenty of resources.

    regards,

    Joseph

Reply
  • For chip production tests, usually for logic (i.e. the processor and the processor system logic excluding RAM) should be tested using scan tests. Before tape out, you should also run LEC (Logic Equivalent Checking) to ensure that that netlist matching the RTL.

    For memory macros, you can add memory BIST (this is done outside of processors). You need to check the EDA tool manuals on how to do that. You could run software based memory tests, but there is an issue - if the chip is bad, how can you be sure the software to test memory is running correctly?

    If you google for "memory testing algorithms" you should find plenty of resources.

    regards,

    Joseph

Children