How to verify the Cortex-M0 thumb instructions ? I found one chip( RAM &FLASH is OK) when it run LDR relative instructions,the program is in Hardfault。But others run the same code is OK

We have run the code on an FPGA，the result of R2 is 0x08. But only the one chip is bad, others run the same code is OK。We try to pick pu bad chips which have the same problems, when  test chip in FT. But we don't know  how to check the functions of CM0,Can you give me some methods?

We have run the code on an FPGA，the result of R2 is 0x08. But only the one chip is bad, others run the same code is OK。We try to pick pu bad chips which have the same problems, when  test chip in FT. But we don't know  how to check the functions of CM0,Can you give me some methods?

For chip production tests, usually for logic (i.e. the processor and the processor system logic excluding RAM) should be tested using scan tests. Before tape out, you should also run LEC (Logic Equivalent Checking) to ensure that that netlist matching the RTL.

For memory macros, you can add memory BIST (this is done outside of processors). You need to check the EDA tool manuals on how to do that. You could run software based memory tests, but there is an issue - if the chip is bad, how can you be sure the software to test memory is running correctly?

If you google for "memory testing algorithms" you should find plenty of resources.

regards,

Joseph

the memory and flash of  bad chip is good , We have  tested them. We have tested CM0 logic by DFT, but is ok. Only the instructions (SUBS R2,R2,R4 ) is wrong, no matter the SUBS in SRAM or FLash

Is this a timing path issue? Does it fail when running at lower frequency?

In general we expected DFT to pick up this kind of issues. There are some limitations with DFT, for example, timing violations might not be picked up by DFT because scan clock usually run slower, and defects could be hidden as clock signal's characteristic could be very different in scan mode. But test coverage of software tests are usually much lower than DFT.  In general, DFT is the recommended test method.

regards,

Joseph

This is a timing issue, when  it runs at lower frequency,the result of  SUBS R2,R2,R4 is correct.So we want to pick up those bad chips by running code. But how to pick up?

Can you do at-speed test with scan chains?

Never do this before，How to do at-speed test with scan chins？

It is similar to normal DFT scan test, but the capture cycle (gap between last shift to capture clock edge) is using normal clock speed.

https://www.eetimes.com/document.asp?doc_id=1217753

Thank you very much!