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Cortex-R prefetch behavior? Does it cross page boundary?

Yaniv

Hi,

I am looking on some info on prefetch (of instruction) in cortex-r.

I have a very inefficient (power wise) memory which usually is not access, even with branch predictor I will have many unneeded accesses.

In some older ARM architecture there was a known note it can not cross 1-KB boundary. Is there any known (published) statement for cortex-R?

Thanks,

Yaniv

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  • 0 Arm Employee Badge

    Which Cortex-R processor(s)?

    In ARMv7-R the processor can speculatively fetch an instruction from any address marked as executable (*).  Whether a given processor will do so, and under what circumstances, is a micro-architectural question.

    If you could avoid placing any instructions in the slow memory you could then mark it as XN (execute never).  This would prevent speculative instruction fetches.

    (* See section B5.2.1 of the ARMv7-A/R Architecture Reference Manual rev C.c)

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  • 0 Arm Employee Badge

    Which Cortex-R processor(s)?

    In ARMv7-R the processor can speculatively fetch an instruction from any address marked as executable (*).  Whether a given processor will do so, and under what circumstances, is a micro-architectural question.

    If you could avoid placing any instructions in the slow memory you could then mark it as XN (execute never).  This would prevent speculative instruction fetches.

    (* See section B5.2.1 of the ARMv7-A/R Architecture Reference Manual rev C.c)

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