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We know that a Cortex-M0 or any other Cortex-M may have fewer interruptions implemented the architecture defined in the standard, so we can not use interrupts implemented as software interrupts by manipulating the registers SETENA / ClrEnable and SetPend / ClrPend.
For example, being the interrupt # 5 (Exception # 21) not implemented at the hardware level, this could be used as an interrupt / exception of software?
Hi Carlos-san,
is to use NVIC_ISPR register for occurring the interrupt #5 not your intention?
For example,
*(int*)0xe000e100=(1<<5); // Interrupt enable*(int*)0xe000e200=(1<<5); // Interrupt pending.
Best regards,Yasuhiko Koumoto.