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We know that a Cortex-M0 or any other Cortex-M may have fewer interruptions implemented the architecture defined in the standard, so we can not use interrupts implemented as software interrupts by manipulating the registers SETENA / ClrEnable and SetPend / ClrPend.
For example, being the interrupt # 5 (Exception # 21) not implemented at the hardware level, this could be used as an interrupt / exception of software?
If I understand the question correctly, you want to create an interrupt service routine (for instance a timer or a DMA-completion routine), which uses an unused interrupt vector in the exception vector area, thus you will be emulating an interrupt, is that understood correctly ?
I believe you may store anything you like in unused vectors, even counter-values and other variables.
(The answers below says that it's possible to trigger the interrupt by setting the pending bit on some implementations, so hereby I correct my answer to inform that there's of course no need to go the extra mile and execute the code manually if the microcontroller supports the triggering via the pending-bit).