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CPU Reset during a Debug session

Kashif

Hi All,

I am trying to reset the CPU in the middle of a debugging session. I am using Application Interrupt and Reset control register by setting the SysResetReq bit in the SCB block. (this preserves the current debugging session also).

However, as I am using ASM its a bit cumbersome.  This is the code snippet I am trying to use..

AIRCR   EQU 0xE000ED0C.

.

ldrr10, =0x05FA0000
LDRR8, =AIRCR ;
STRR8, [R10];

Any feedback/input help will always be appreciated.

Thanks!!

BR,

\ksnf3000

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  • +1 Arm Employee Badge in reply to Kashif

    This excerpt is from the ARM Architecture, so some behaviours are implementation-defined.  You need to look at the documentation for your specific system.

    In general though I'm not sure I understand your problem.  You have a halting debug session and you want to trigger a reset of the CPU.  To this end you embed instructions to request a reset, which will cause execution to resume at the reset handler.  This is the behaviour defined by the architecture.  You can continue to debug, but you have effectively thrown away your program state because you triggered a reset.

    So, what problem are you trying to solve?

Reply
  • +1 Arm Employee Badge in reply to Kashif

    This excerpt is from the ARM Architecture, so some behaviours are implementation-defined.  You need to look at the documentation for your specific system.

    In general though I'm not sure I understand your problem.  You have a halting debug session and you want to trigger a reset of the CPU.  To this end you embed instructions to request a reset, which will cause execution to resume at the reset handler.  This is the behaviour defined by the architecture.  You can continue to debug, but you have effectively thrown away your program state because you triggered a reset.

    So, what problem are you trying to solve?

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  • 0 in reply to Jon Black

    Well this is the problem I'm trying to solve actually.I want to preserve the SRAM contents of my system so that even after a soft-reset (done by the program), I am able to view the SRAM contents effectively from the point where I left the system at reset. The interval between the reset and the accessing of the SRAM will be varied later.

    Thanks!

  • 0 Arm Employee Badge in reply to Kashif

    The state of SRAM in your system after a soft reset will be determined by the design of your specific system.  You need to consult the manufacturer's documentation for that.

    If I understand correctly, your software requires the ability to initiate a soft reset while preserving some amount of state in the SRAM.  Is this data or are you executing out of SRAM at this point?  You have suggested earlier that you would like the system to resume execution where it left off after triggering the reset.  This is not the behaviour of the hardware so you would need to implement your software such that after the reset handler has executed and you have re-initialised your CPU, you pick up the state and resume whatever processing you suspended to do the reset.