CPU Reset during a Debug session

If you only want to reset CPU (excluding its debug components), possibly you can try to set VECTRESET bit in Application Interrupt and Reset Control Register.

Thanks Stevens. Could you/anyone possibly let me know how to set this specific bit using ASM?

Hi

LDR R0,=0xE000ED0C

LDR R1,=0x05fa0001

STR R1,[R0]

I hope this helps

Ali

Hi Ali/All,

I tried the same thing. However, I used registers R9 and R10. But it fails to write to them as you can see in the snapshot below. and at the beginning of the code I used  AIRCR EQU 0xE000ED0C

Also, I used the value 0xfa050001, which I see is different in representation from yours.

Please advice.

Thanks!

BR,

\Kashif

Hi Ali,

On using the value provided by you (0x05fa0001), I noticed something interesting. After the STR instruction, the debugger jumps back to the LDR instruction of loading the AIRCR address (LDR R0,=0xE000ED0C)  and clears the R9 and R10 registers.

Is this a reset? looks like one,because its in a loop but I don't exactly get what is happening.

Thanks!

BR,

\Kashif

Hi

-AIRCR :  (Register writes must write 0x05FA otherwise the write is ignored ,On reads Returns 0xFA05 ).

-After the STR instruction, the Debugger jumps back to the  Reset_Handler.

BR,

Ali

Hi Ali,

Thanks!! but sadly, I cant see this behavior happening in my code. I even commented all my code and used exactly the part which is mentioned in your code but still no results.

Is it due to the different set of registers I maybe using? I am using R10 to load the AIRCR value and R9 for storing the 0x05FA0001?

BR,

\Kashif

Hi Ali,

It works if I add a small segment of code like a delay loop. Don't know why!!

So, now is there a way I can come out of this reset/startup? I mean I want that the CPU only resets once and then resumes say from the LDR R5 instruction. Any ideas on how can this be achieved?

BR,

\Kashif

Hi Kashif

__ " It works if I add a small segment of code like a delay Loop. Don't  know why!!"

  delay is to Wait until reset happen (How many cycles is device-specific);

__ after a reset ,program execution always start at Reset _Handler

BR,

Ali

Yeah got it!! Thanks!

Also, could you provide your input on my 2nd query? "So, now is there a way I can come out of this reset/startup? I mean I want that the CPU only resets once and then resumes say from the LDR R5 instruction. Any ideas on how can this be achieved?"  Means that I want this reset to happen only ONCE everytime the code runs and then come out of this reset loop and continue working.

BR,

\Kashif

I am trying something like this but I dont think its working.

The SYS_NVFLAGSSET, as I understand, is a general purpose flag register. I am trying to set its flag so that on reset it checks the value and comes out of this reset loop. Not sure if this is right.

BR,

\Kashif

Hi Jon,

Thanks for your reply. However, I did observe that the debugger points to the Reset_handler in the startup code once the code has run (without providing a local request). Strange, or is there something that I maybe missing?

Would be glad if you can clarify this?

My query is that I would like to implement a conditional CPU reset i.e only once should the CPU reset and after reset it should continue from where it stopped (since its in the debug mode) and not enter a reset loop.

BR,

\Kashif

When your CPU has taken the reset, execution will resume from your defined reset handler.  At this point you will by definition have exited from your reset wait loop.

From the ARMv6-M Architecture Reference Manual:

7.5.16. Reset management

In ARMv6-M, the AIRCR provides a mechanism for a system reset, see Application Interrupt and Reset Control Register, AIRCR.  Setting the AIRCR.SYSRESETREQ control bit to 1 requests a reset by an external system resource. The system components that are reset by this request are implementation defined. A Local reset is required as part of a system reset request.

Setting the SYSRESETREQ bit to 1 does not guarantee that the reset takes place immediately. A typical code sequence to synchronize reset following a write to the relevant control bit is:

      DSB; 
Loop  B    Loop; 

This excerpt is from the ARM Architecture, so some behaviours are implementation-defined.  You need to look at the documentation for your specific system.

In general though I'm not sure I understand your problem.  You have a halting debug session and you want to trigger a reset of the CPU.  To this end you embed instructions to request a reset, which will cause execution to resume at the reset handler.  This is the behaviour defined by the architecture.  You can continue to debug, but you have effectively thrown away your program state because you triggered a reset.

So, what problem are you trying to solve?