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ARM926ejs Cache linefill

guestposter guestposter
  • 0
    Note: This was originally posted on 25th March 2009 at http://forums.arm.com

    Hi isogen74:

         Thank you for your reply .

         in my system, i really use the write-back mode, i post question using write-though mode only because i want to know exactly what is the meaning of "buffered store to external memory".

         i am sorry that i still can not understand how to buffered store to external momory. does it mean that when write cahce hit, data first updated in DCache, and then send data to write buffer, and after a little time, we assue it is 1us, the data in write buffer is updated to SDRAM automatically.

    >All ARM9 caches are read-allocate. A write that misses will not update the cache.

           in my mind, i think write miss should of course do linefill immediately, why doesn't ARM implement this on ARM9? is it because of cost?  and in arm11, is this implemented?


           another question:  in ARM9 TRM, it said as below:

    The write buffer is used for all writes to a noncachable, bufferable region, write-through
    region, and write misses to a write-back region. A separate buffer is incorporated in the
    DCache for holding write-back data for cache line evictions or cleaning of dirty cache
    lines.
    The main write buffer has a 16-word data buffer and a four-address buffer.
    The DCache write-back buffer has eight data word entries and a single address entry.
    The MCR drain write buffer instruction enables both write buffers to be drained under
    software control.
        
          does it mean that there are two physical write buffer on ARM9, one is specifically for CPU STR instruction which may write data to SDRAM, and the other is epecifically for DCache?


    Best Regards
  • 0
    Note: This was originally posted on 25th March 2009 at http://forums.arm.com

    Hi isogen74:

         thank you very much for explaining this to me patiently .

       

    Best Regards
  • 0 Arm Employee Badge
    Note: This was originally posted on 25th March 2009 at http://forums.arm.com

    > in my system, i really use the write-back mode, i post question using write-though mode only because i want to know exactly what is the meaning of "buffered store to external memory".

    Buffering just means that the core can (probably) proceed with useful work without waiting for the actual write to hit external memory. The actual implementation of buffering varies from core to core - but in most cases there is a  general write buffer for small writes and an optimized write buffer for cache-line evictions. (As you mention at the bottom of your post)

    > Does it mean that when write cahce hit, data first updated in DCache, and then send data to write buffer, and after a little time, we assue it is 1us, the data in write buffer is updated to SDRAM automatically.

    Yes, that sounds right to me. Microarchitectures vary slightly so some systems may issue cache update and external DRAM write in parallel.

    > In my mind, i think write miss should of course do linefill immediately, why doesn't ARM implement this on ARM9? Is it because of cost?

    I suspect so ... the usual arguments for not doing something are related to power, silicon area and meeting cache timing constraints.

    > and in arm11, is this implemented?

    ARM11 MPCore and Cortex-A* cores implement write allocate caches. I'm not sure about the Cortex-R4 - I've never used one :)

    > Does it mean that there are two physical write buffer on ARM9, one is specifically for CPU STR instruction which may write data to SDRAM, and the other is epecifically for DCache?

    Yes. The cache writebuffer is optimized because it only ever has to handle half-line length bursts which are always naturally aligned.
  • +1 Arm Employee Badge
    Note: This was originally posted on 25th March 2009 at http://forums.arm.com

    > If not, how can we make sure the coherence of DCache and SDRAM when in Write-though mode?

    Here you are basically trying to assume coherence between to memories with radically different timing properties - assuming other bus masters can access the DRAM, and that the DRAM is clocked slower than the cache you might be waiting some time for the DRAM write to complete. I think you would have to perform a drain write-buffer operation to ensure coherence.

    Is there any particular reason why you want to use write-through rather than write-back? Write-back is normally much more power efficient, and more bus bandwidth friendly - and adding the necessary cache maintenance operations to synchronize with external memory is not normally too difficult.

    > When arm9 write a write-though region, if cache miss, will it first fill the cache line, then write
    data to DCache, and at last send to from DCache to Write Buffer? 

    All ARM9 caches are read-allocate. A write that misses will not update the cache.

    Cheers, I